1. Technical Field
The present invention generally relates to digital data processing systems and, more particularly, to digital data processing systems employing a plurality of RAM (Random Access Memory) blocks.
2. Description of Related Art
Data processing systems usually have storage components such as RAMs (dynamic RAMs (DRAMs) or static RAMs (SRAMs)). The RAMs are installed in a circuit board together with a microprocessor (or a microcontroller) in a digital data processing system. A large capacity RAM is divided into plural blocks of uniform memory capacities for operating at a high clock frequency.
Such systems having plural RAM blocks have been employed with an operational mechanism for operating at a high clock frequency in which RAM blocks in a standby state as well as RAM blocks in an operating state are put into a conductive state, to secure the minimum setup times necessary to make the standby RAM blocks operable in an operating state. As a result, there has been unnecessary power consumption in the system due to current through the standby RAM blocks. The rate of power consumption increases as the memory capacity of the RAM is increased.
Another conventional way to reduce unnecessary power consumption is to force RAM blocks that are not going to be used in an operation into a standby state. Therefore, setup times are required to operate newly selected RAM blocks in order to switch a memory access routine from the conductive RAM blocks in an operating state to the RAM blocks in a standby state. Securing the setup times is accomplished by controlling an operation speed of a microprocessor for a period of time when a signal for selecting a RAM block is active. Thus, a frequency-divided signal of a master clock provided from an oscillator is applied to the microprocessor. Consequently, the overall speed of a digital data processing system is degraded so that an operation speed of the microprocessor declines when a memory access routine switches from the RAM blocks in an operating state to the RAM blocks in a standby state.
To solve the above and other related problems of the prior art, there is provided a digital data processing system having plural RAM blocks. The digital data processing system according to the invention reduces overall power consumption as well as enhances operational efficiency without unnecessary power consumption.
According to an aspect of the present invention, there is provided a digital data processing system that comprises an oscillator, a plurality of memory blocks, a processor, and an access controller. The oscillator generates a clock signal with a predetermined frequency. The processor conducts access operations for the memory blocks in response to the clock signal. The access controller inhibits an access operation for a selected one of the plurality of memory blocks when the selected one of the plurality of memory blocks is being setup by the processor.
The present invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.